VIN DTS配置
昉·惊鸿-7110
SoC平台的一般配置文件在以下路径：
linux/arch/riscv/boot/dts/starfive/jh7110.dtsi以下代码块显示了VIN DTS配置文件的内容。
vin_sysctl: vin_sysctl@19800000 { compatible = "starfive,jh7110-vin"; reg = <0x0 0x19800000 0x0 0x10000>, <0x0 0x19810000 0x0 0x10000>, <0x0 0x19820000 0x0 0x10000>, <0x0 0x19840000 0x0 0x10000>, <0x0 0x19870000 0x0 0x30000>, <0x0 0x11840000 0x0 0x10000>, <0x0 0x17030000 0x0 0x10000>, <0x0 0x13020000 0x0 0x10000>; reg-names = "csi2rx", "vclk", "vrst", "sctrl", "isp", "trst", "pmu", "syscrg"; clocks = <&clkisp JH7110_DOM4_APB_FUNC>, <&clkisp JH7110_U0_VIN_PCLK>, <&clkisp JH7110_U0_VIN_SYS_CLK>, <&clkisp JH7110_U0_ISPV2_TOP_WRAPPER_CLK_C>, <&clkisp JH7110_DVP_INV>, <&clkisp JH7110_U0_VIN_CLK_P_AXIWR>, <&clkisp JH7110_MIPI_RX0_PXL>, <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF0>, <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF1>, <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF2>, <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF3>, <&clkisp JH7110_U0_M31DPHY_CFGCLK_IN>, <&clkisp JH7110_U0_M31DPHY_REFCLK_IN>, <&clkisp JH7110_U0_M31DPHY_TXCLKESC_LAN0>, <&clkgen JH7110_ISP_TOP_CLK_ISPCORE_2X>, <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>; clock-names = "clk_apb_func", "clk_pclk", "clk_sys_clk", "clk_wrapper_clk_c", "clk_dvp_inv", "clk_axiwr", "clk_mipi_rx0_pxl", "clk_pixel_clk_if0", "clk_pixel_clk_if1", "clk_pixel_clk_if2", "clk_pixel_clk_if3", "clk_m31dphy_cfgclk_in", "clk_m31dphy_refclk_in", "clk_m31dphy_txclkesc_lan0", "clk_ispcore_2x", "clk_isp_axi"; resets = <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_P>, <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_C>, <&rstgen RSTN_U0_VIN_N_PCLK>, <&rstgen RSTN_U0_VIN_N_SYS_CLK>, <&rstgen RSTN_U0_VIN_P_AXIRD>, <&rstgen RSTN_U0_VIN_P_AXIWR>, <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF0>, <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF1>, <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF2>, <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF3>, <&rstgen RSTN_U0_M31DPHY_HW>, <&rstgen RSTN_U0_M31DPHY_B09_ALWAYS_ON>, <&rstgen RSTN_U0_DOM_ISP_TOP_N>, <&rstgen RSTN_U0_DOM_ISP_TOP_AXI>; reset-names = "rst_wrapper_p", "rst_wrapper_c", "rst_pclk", "rst_sys_clk", "rst_axird", "rst_axiwr", "rst_pixel_clk_if0", "rst_pixel_clk_if1", "rst_pixel_clk_if2", "rst_pixel_clk_if3", "rst_m31dphy_hw", "rst_m31dphy_b09_always_on", "rst_isp_top_n", "rst_isp_top_axi"; starfive,aon-syscon = <&aon_syscon 0x00>; power-domains = <&pwrc JH7110_PD_ISP>; /* irq nr: vin, isp, isp_csi, isp_scd, isp_csiline */ interrupts = <92 87 88 89 90>; status = "disabled"; }; &vin_sysctl { status = "okay"; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; #address-cells = <1>; #size-cells = <0>; /* Parallel bus endpoint */ parallel_from_sc2235: endpoint@0 { reg = <0>; remote-endpoint = <&sc2235_to_parallel>; bus-type = <5>; /* Parallel */ bus-width = <8>; data-shift = <2>; /* lines 9:2 are used */ hsync-active = <1>; vsync-active = <1>; pclk-sample = <1>; status = "okay"; }; }; port@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; /* CSI2 bus endpoint */ csi2rx0_from_ov4689: endpoint@0 { reg = <0>; remote-endpoint = <&ov4689_to_csi2rx0>; bus-type = <4>; /* MIPI CSI-2 D-PHY */ clock-lanes = <0>; data-lanes = <1 2 3 4>; status = "okay"; }; /* CSI2 bus endpoint */ csi2rx0_from_imx219: endpoint@1 { reg = <1>; remote-endpoint = <&imx219_to_csi2rx0>; bus-type = <4>; /* MIPI CSI-2 D-PHY */ clock-lanes = <0>; data-lanes = <2 1>; lane-polarities = <1 1 1>; status = "okay"; }; csi2rx0_from_imx708: endpoint@2 { reg = <2>; remote-endpoint = <&imx708_to_csi2rx0>; bus-type = <4>; /* MIPI CSI-2 D-PHY */ clock-lanes = <0>; data-lanes = <2 1>; lane-polarities = <1 1 1>; status = "okay"; }; }; }; };
以下为上述代码块的参数说明：
- compatible：兼容性信息，用于连接驱动程序和目标设备。
- reg：寄存器基本地址“0x19800000”和范围“0x10000”。
- reg-names：VIN模块使用到的寄存器名称。
- clocks：所需要的clocks。
- clock-names：上述时钟的名称，需要和驱动中定义的相同。
- resets： VIN模块使用到的复位信号。
- reset-names：上述复位信号的名称。
- power-domains：电源域。
- interrupts：硬件中断ID。
- status：VIN模块的工作状态。要启用模块，请将此位设置为“okay”；要禁用该模块，请将此位设置为“disabled”。